The present invention relates to a electrically erasable programmable read-only memory (EEPROM) and, more specifically, to a NAND stack EEPROM.
In general, a computer system is comprised of a memory for holding data and programs, a processor for executing the programs or operating on the data held in memory, and an input/output device for facilitating communications between the computer system and a user. There are several different types of digital memories available for use in the memory portion of a computer system. In many instances, the particular application in which the computer system is intended to be used dictates the type of memory that is appropriate for all or a portion of the memory of the computer system. For instance, one application for a computer system in which a NAND stack EEPROM may be appropriate is in a portable computer system. Portable computer systems are generally designed to operate, if needed, with power supplied by a battery housed within the system. If the battery becomes incapable of providing power to the system and an alternative source of power is not available, the data held in memory could become irretrievably lost. In such applications, it may be desirable to employ a EEPROM memory because an EEPROM is capable of retaining data even when power is not being provided.
A typical EEPROM memory device is comprised of: (1) a plurality of EEPROM memory cells; (2) an input/output structure for transferring data between the memory cells and the exterior environment and receiving commands relating to such transfers; and (3) a controller that, in response to commands, causes data to be transferred between the memory cells and the exterior environment via the input/output structure. More recently, xe2x80x9cNANDxe2x80x9d type EEPROMs have evolved in which a plurality of EEPROM memory cells are connected in series to form a xe2x80x9cstack.xe2x80x9d One end of the stack is connected to a bit line that is used to transfer bits of data between each of the EEPROM memory cells in the stack and the exterior environment. The other end of the stack is connected to ground. The advantage of the NAND stack EEPROM is that, relative to EEPROMs that do not employ a stack, greater memory density can be achieved, i.e., there are a greater number of EEPROM memory cells per unit area. Additionally, NAND stack EEPROMs also are less expensive to manufacture than EEPROMs that do no employ the stack architecture.
However, a drawback associated with many NAND stack EEPROM devices is that bits must be programmed or written into the memory cells in the stack in sequence, i.e., the memory cell closest to ground must be programmed first, then the memory cell next closest to ground is programmed and so on until the memory cell furthest from ground is programmed. Similarly, the bits in the memory cells in the stack must be read in the reverse order in which they were programmed. In programming a bit into a particular memory cell in the stack, it is necessary, while the programming is occurring, to prevent the bits in the other memory cells in the stack from being disturbed or altered. Many of the NAND stack EEPROMs prevent these bits from being disturbed by utilizing a static program inhibit technique that forces a voltage on the silicon surface adjacent a cell that is about equal to the voltage on the gate of the field-effect transistor that constitutes the memory cell. As a consequence, the potential drop across the dielectric of the transistor is insufficient to produce the tunneling of charge that would otherwise program the transistor.
The present invention provides a NAND stack EEPROM that allows the memory cells within the stack to be programmed in any order. For example, in a NAND stack EEPROM that has two, series-connected, memory cells with the first memory cell located closer to ground than the second memory cell, a bit can be programmed into the second memory cell before a bit is programmed into the first memory cell or visa versa. In other words, the present invention provides a NAND stack EEPROM that is capable of random programming of the memory cells in the stack.
Random programming of the memory cells in the stack is achieved in one embodiment by utilizing a dynamic program inhibit rather than the previously noted static program inhibit. In dynamic program inhibit, the silicon surface of the EEPROM is disconnected from all sources of charge such that the surface can then couple up with the gate of the field-effect transistor that constitutes a memory cell. This coupling, in turn, produces a potential drop across the dielectric of the EEPROM that is insufficient to cause the tunneling of charge that would program the transistor. It should be appreciated that dynamic program inhibit is a dynamic or transitory phenomena that only exists for relatively short period of time. Consequently, any programming must be completed while the dynamic program inhibit is in effect. In contrast, static program inhibit lasts until the voltage on the silicon surface is removed.
A NAND stack EEPROM with dynamic program inhibit capability has number of advantages relative to a NAND stack EEPROM with static program inhibit. Namely, a NAND stack EEPROM with dynamic program inhibit has the advantages of: (1) allowing random programming of the series-connected memory cells in a stack; (2) reducing the number of nodes within the stack to which high voltage must be applied; and (3) allowing the spacing between circuit elements to be reduced, thereby permitting a greater density of memory cells for a given area.